The newest version of Transputer architectured chips is the INMOS T-9000, a processor containing 4 serial links, designed to be hooked up to other processors for parallel processing. The instruction set is minimized, as is the Sparc's RISC design, but is "based on a stack/accumulator design and designed around the OCCAM language". each chip containing 4 serial links to connect the chips in a network.The T-9000 was an attempt to regain the lead after more recent chips have surpassed previous transputers. The T-9000 basic architecture is that of the T-800 which contains "three 32 bit integer and three 64 bit floating point registers which are used as an evaluation stack - they are not general purpose." It uses memory addressed relative to the workspace, so access is slowed down with every 4 bits used for offset from the workspace register. The T-9000 has several levels of high speed caches and memory types, because of it's overwhelming speed. "The main cache is 16K, and is designed for 3 reads and 1 write simultaneously. The workspace cache is based on 32 word rotating buffers, allows 2 reads and 1 write simultaneously."The stack architecture makes instructions, in bytes, very compact, but executing one instruction byte per clock can be slow for multibyte instructions, so the T-9000 has a grouper which gathers instruction bytes (up to eight) into a single CISC-type instruction then sent into the 5 stage pipeline.This processor is ideal for parallel processing, " known as systolic arrays" (a pipeline is a simple example). Large networks can be created with the C104 crossbar switch, which can connect 32 transputers or other C104 switches into a network. "Transputers can adapt to a 64, 32, 16, or 8 bit bus. They can also feed off a 5 MHz clock, generating their own internal clock from this signal, and contain internal RAM, making them good for high performance embedded applications."However big delays in the T-9000 design "partly because of the stack based design"(T-9000) left it in the dust competitively with other CPUs .SPARC, Scalable Processor ARChitecture, was designed by Sun Microsystems for their own use. Existing manufacturers were slow to introduce a RISC processor, so Sun, a maker of workstations,went ahead and developed its own, based on Berkley's design and lesed it's design to other manufacturers.The original SPARC design was very unique, "even omitting multiple cycle multiply and divide instructions" which were added in later versions. SPARC usually contains about 128 or 144 registers. At each time 32 registers are available 8 are global, the rest are allocated in a 'window' from a stack of registers." The window is moved 16 registers down the stack during a function call, so that the upper and lower 8 registers are shared between functions, to pass and return values, and 8 are local. The window is moved up on return, so registers are loaded or saved only at the top or bottom of the register stack."
This allows functions to be called in as little as 1 cycle. "Like most RISC processors SPARC is pipelined for performance. Also like previous processors, a dedicated CCR holds comparison results. SPARC is "scalable" mainly because the register stack can be expanded, to reduce loads and saves between functions, or scaled down to reduce interrupt or context switch time, when the entire register set has to be saved. Function calls are usually much more frequent than interrupts, so the large register set is usually a plus, but compilers now can usually produce code which uses a fixedregister set as efficiently as a windowed register set across function calls.""SPARC is not a chip, but a specification," therefore many designs exist. It has undergone revisions, and other than having multiply and divide instructions. Version 8 specified 32 bit implementation whereas version 9 supports 64 bits, and superscalar versions were designed and implemented , still not enough to keep up with other load-store processors. Then 2 new processors were designed, the UltraSPARC in late 1995 from Texas Instruments and Sun, and superscalar HAL/Fuji SPARC64 multichip CPU. (Sun Microsystems: ) "The UltraSPARC is a 64-bit superscalar processor series which can issue up to four instructions at once to any of nine units: two integer units, two of the five floating point/graphics units, the branch and load/store unit. The UltraSparc also added a block move instruction which bypasses the caches, to avoid disrupting it, and specialized pixel operations which can operate in parallel on 8, 16, or 32-bit integer values packed in a 64-bit floating point register". (Sun Microprocessor Products: ) "The HAL/Fuji SPARC64 can issue up to four in order instructions simultaneously to four buffers, then to four integer, two floating point, two load/store, and the branch unit, and may complete out of order. An instruction completes when it finishes without error, is committed when allinstructions ahead of it have completed, and is retired when its resources are freed - these are 'invisible' stages in the SPARC64 pipeline. A combination of register renaming, a branch history table, and processor state storage allow for speculative execution while maintaining precise exceptions/interrupts (renamed integer, floating, and CC registers - trap levels are also renamed and canbe entered speculatively)." (HAL Computer Systems, Inc. )