Modern digital systems require the capability of storing and retrieving large amounts of information at high speeds. Memories are circuits or systems that store digital information in large quantity. Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The amount of memory required in particular system depends on the type of the application. These semiconductor memories are also known as VLSI memories.
Surveys indicate that roughly 30% of the worldwide semiconductor business is due to memory chips. Over the years, technology advances have been driven by memory designs of higher and higher density. Data storage capacity available on a single integrated circuit grows exponentially being doubled approximately every two years.
Types of Memories:
Semiconductor memory is generally classified according to the type of data storage and data access. While each form has a different cell design, the basic structure, organization, and access mechanisms are largely the same.
Read/Write Memory or Random Access Memory (RAM):
R/W memory permits the modification (write operation) of data bits stored in the memory array, as wells as their retrieval (read operation). The read/write memory is commonly known as Random Access Memory. Based on the operation type of individual cells read/write memory is further divided into Dynamic RAM (DRAM) and Static RAM (SRAM).
As the name implies, read-only memory also only retrieval of previously stored data and does not permit modifications o the stored information contents during normal operation. Depending o the type of data storage (data writing operation), ROMs are classified into different types as shown above.
In Mask ROM, the data is written during chip fabrication using the photo mask. In programmable ROM, data is written electrically after the chip fabrication. Depending on the way data is erased, PROMs are further classified into different types- fuse ROMs, EPROMs and EEPROMs.
There are two more types of memories known as flash memory and Ferroelectric RAM (FRAM). Flash memory is similar to EEPROM in terms of data erasing operation.
Read/Write or Random Access Memory
Ferroelectric RAM (FRAM)
Electrically erasable PROM
Programmable ROM (PROM)
Mask programmed ROM
Static RAM (SRAM)
Dynamic RAM (DRAM)
Now a days almost all the memories are being produced on MOSFET based transistors. But it is not the same or all the applications. In high-density and high-speed applications, various combinations of bipolar and MOS technologies are being used. In addition to MOS and bipolar memories, there are also other memory technologies being developed.
Electronic memory capacity in digital systems ranges from fewer than 100 bits for a simple function to standalone chips containing 256 Mb (1 Mb = 210 bits) or more. Circuit designers usually speak of memory capacities in terms of bits, since a separate flip-flop or other similar circuit is used to store each bit. On the other hand, system designers’ usually state memory capacities in terms of bytes (8 bits); each byte represents a single alphanumeric character.
Very large scientific computing systems often have memory capacity stated in terms of words (32 to 128 bits). Each byte or word is stored in a particular location that is identified by a unique numeric address. Memory storage capacity is usually stated in units of kilobytes (K bytes) or megabytes (M bytes). Because memory addressing is based on binary codes, capacities that are integral powers of 2 are most common. Thus the convention is that, for example, 1K byte =1,024 bytes and 64K bytes = 65,536 bytes. In most memory systems, only a single byte or word at a single address is stored or retrieved during each cycle of memory operation.
Key Design Criteria:
The following are the key design criteria that determine the overall storage capacity, memory speed and power consumption:
The area efficiency of the memory array, i.e., the number of stored data bits per unit area, determines the memory cost per bit.
The memory access time, i.e., the time required to store and/or retrieve a particular data bit in the memory array which determines the memory speed.
The static and dynamic power consumption of the memory array.
Circuits of Memory Cells:
A semiconductor memory consists of memory cells. Each memory cell is able to store one bit. Figure 1.1 and figure 1.2 shows the equivalent circuits of memory cells. Each type of memory cell has its own structure. The circuits mainly consist of MOSFETs and capacitors.
The DRAM cell shown in figure 1.1(a) consists of a capacitor and a switch transistor. The data are stored in the capacitors as presence and absence of charge: The presence of charge in the capacitor is considered as data “1” while the absence of charge in the capacitor as data “0”. The stored charge decays gradually due to leakage current. Thus refresh operation is required and because of this refresh operation, it is known as dynamic memory. This type of structure results in having high density.
Figure 1.1 Equivalent circuits of memory cells. (a) DRAM, (b) SRAM
The SRAM cell shown in figure 1.1(b) has six-transistor bistable latch structure to hold the state of each cell node. A typical SRAM uses six MOSFETs to store each memory bit. There are other types of SRAM memory cells which use 8, 10, or more transistors depending on the applications. The refresh operation is not needed in SRAMs because, the cell data can be held at one of the two possible states as long as power supply is provided.
In Mask ROM cell shown in the figure 1.2(a), the data are programmed by a Mask pattern, blowing out the fuse located at each cell. Only one-time programming operation is allowed. In the EPROM and EEPROM, data can be rewritten into the cell by using ultraviolet rays or by a tunnel current, respectively. The blocks of the memory may be erased simultaneously. EPROMs are easily recognizable by the transparentA fused quartzA window in the top of the package, through which the silicon chip can be seen, and which permits UV light during erasing. Their large storage capacity has made them an emerging mass storage medium.
Figure 1.2 Equivalent circuits of memory cells. (a) Mask ROM, (b) EPROM (EEPROM), (c) FRAM
The FRAM or FeRAM cell has the similar structure that of DRAM except the ferroelectric capacitor, where the cell data are modified by changing the polarization of ferroelectric material. The Perovskite crystal material used in the memory cells of this type of RAM can be polarized in one direction or the other to store the desired value. The polarization is retained even when the power supply is removed, thereby creating a nonvolatile memory.
The preferred memory array organization is shown in the Fig. 1.0. This organization is random-access architecture. The name is derived from the fact that memory locations (address) can be accessed in random order at a fixed rate, independent of physical location, for reading or writing. The data storage structure, or core, consists of individual memory cells arranged in an array of horizontal rows and vertical columns. Each cell is capable of storing one bit of binary information. Also, each memory cell shares a common connection with the other cells in the same row, and another common connection with other cells in the same column. In this structure, there are 2N rows, also called word lines, and 2M columns, also called bit lines. The bit selection is done using a multiplexer circuit to direct the corresponding cell outputs to data registers. Thus the total number of memory cells in this array is 2N X 2M .
Figure 1.0 Conceptual random-access memory array organization.
To access a particular memory cell, i.e., a particular data bit in this array, the corresponding word line and the corresponding bit line must be activated (selected) according to the addresses coming from the outside of the memory array. These addresses are provided by the memory controller or the processor directly. The row and column selection operations are accomplished by row and column decoders, respectively. The row decoder circuit selects one out of 2N word lines according to an N-bit row address, while the column decoder selects one out of 2M bit lines according to an M-bit column address.
This organization can be used for both read/write memory arrays and read-only memory arrays.
Static Random Access Memory (SRAM):
Static Read/Write (or Random Access) memory (SRAM) is able to read and write data into its memory cells and retain the memory contents as long as the power supply voltage is provided. Currently SRAM are manufactured in the CMOS technology which offers very low static power dissipation, superior noise margin and switching speed.
The cells of the CMOS SRAM are based on a simple latch circuit as shown in Figure 1.0.
Figure 1.0 A six-transistor CMOS SRAM cell. 
The cell consists of six transistors: four nMOS and two pMOS. Two pairs of transistors form a pair of inverters and two nMOS transistors form the access switches. Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. In addition to such 6T SRAM, other kinds of SRAM chips use 8T, 10T, or more transistors per bit.
Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margins.
Types of SRAM:
By transistor type SRAMs can be made of both BJTs and MOSFETs. SRAMs with BJTs are very fast but consume lot of power while the SRAMs with MOSFETs consume less power and are very common today.
By function type SRAMs are classified into asynchronous and synchronous SRAMs.
Operation of SRAM:
In order to consider operation of the static read/write memory we have to take into account:
A?a‚¬A? Relatively large parasitic column capacitances, CC and CC,
A?a‚¬A? Column pull-up pMOS transistors,
Figure 1.0. A CMOS static memory cell with column pull-up transistors and parasitic
column capacitances. 
When none of the word lines is selected, that is, all S signals are ‘0’, the pass transistors n3, n4 are turned off and the data is retained in all memory cells. The column capacitances are charged by the drain currents of the pull-up pMOS transistors, p3, p4.
For the read or write operations we select the cell asserting the word line signal S=’1?.
For the write operation we apply a low voltage to one of the bit line, holding the other one high.
To write ‘0’ in the cell, the column voltage VC is forced to low (C = 0). This low voltage acts through a related pass transistor (n3) on the gates of the corresponding inverter (n2, p2) so that its input goes high. This sets the signal at the other inverter Q = 0.
Similarly, to write ‘1’ in the cell, the opposite column voltage VC is forced to low ( C = 0) which sets the signal Q = 1.
During the read ‘1’ operation, when the stored bit is Q = 1, transistors n3, p1 and n4, n2 are turned on. This maintains the column voltage VC at its steady-state high level (say 3.5V) while the opposite column voltage V A? C is being pulled down discharging the column capacitance CC through transistors n4, n2 so that VC > VC. Similarly, during the read ‘0’ operation we have VC < VC. The difference between the column voltages is small, say 0.5V, and must be detected by the sense amplifiers from data-read circuitry.
Major design effort is directed at minimizing the cell area and power consumption so that millions of cells can be placed on a chip. The steadystate power consumption of the cell is controlled by subthreshold leakage currents, so a larger threshold voltage is often used in memory circuits. To reduce area, the cell layout is highly optimized to eliminate all wasted area.
SRAM Read Operation:
The read operation of the six-transistor SRAM cell as shown in Figure 1.0 is discussed. Assume that a “0” is stored on the left side of the cell, and a “1” on the right side. Therefore, M1 is on and M2 is off. Initially, b and b are precharged to a high voltage around VDD by a pair of column pull-up transistors (not shown in the figure). The row selection line, held low in the standby state, is raised to VDD which turns on access transistors M3 and M4. Current begins to flow through M3 and M1 to ground, as shown in Figure 1.0. The resulting cell current slowly discharges the capacitance Cbit. Meanwhile, on the other side of the cell, the voltage on remains high since there is no path to ground through M2. The difference between b and b is fed to a sense amplifier to generate a valid low output, which is then stored in a data buffer.
Figure 1.0. Six-transistor SRAM cell for ‘read’ operation. 
SRAM Write Operation:
The operation of writing 0 or 1 is accomplished by forcing one bitline, either b or b, low while the other bitline remains at about VDD. In Figure 2.0, to write 1, is forced low, and to write 0, b is forced low. The cell must be designed such that the conductance of M4 is several times larger than M6 so that the drain of M2 is pulled below VS. This initiates a regenerative effect between the two inverters. Eventually, M1 turns off and its drain voltage rises to VDD due to the pull-up action of M5 and M3. At the same time, M2 turns on and assists M4 in pulling output to its intended low value. When the cell finally flips to the new state, the row line can be returned to its low standby level.
Figure 2.0. Six-transistor SRAM cell for ‘write’ operation. 
The design of the SRAM cell for a proper write operation involves the transistor pair M6-M4. As shown in Figure 2.0., when the cell is first turned on for the write operation, they form a pseudo-NMOS inverter. Current flows through the two devices and lowers the voltage at node from its starting value of VDD.
Note that the bitline b- is pulled low before the wordline goes up. This is to reduce the overall delay since the bitline will take some time to discharge due to its high capacitance.
Bipolar SRAM Technologies:
The earliest semiconductor memories were built in bipolar technology. Nowadays, bipolar memories are primarily used in high-speed applications. The following are the bipolar technologies:
Direct-Coupled Transistor Logic (DCTL) Technology
Emitter-Coupled Logic (ECL) Technology
Silicon-on-Insulator (SOI) Technology
Application-specific SRAMs include some extra logic circuitry added to make them compatible for a specific task. Usually, the application-specific SRAMs are made in the high-density, optimized processes which include customized features such as buried contacts and straps to reduce the memory cell size. The following are few of them:
Serially Accessed Memory:
The first-in first-out (FIFO) buffer is an example of the shift register memory architecture through which data can be transferred in and out serially. The FIFOs are generally made using the SRAM cells if there is a requirement for the data to be maintained in the FIFO.
The dual-port RAMs allow two independent devices to have simultaneous read and write access to the same memory. Two devices communicate through common memory. A family of multiport SRAMs with a built-in self-test (BIST) interface has been developed using a synchronous self-timed architecture.
The content-addressable memories (CAMs) are designed and used both as embedded modules on the larger VLSI chips and as a standalone memory for specific systems applications. Unlike the standard memories which associate data with an address, the CAM associates an address with data. The applications using CAMs include database management, disk caching, pattern and image recognition, and artificial intelligence.
DRAM (Dynamic Random Access Memory) is the main memory used for all desktop and larger computers. Each elementary DRAM cell is made up of a single MOS transistor and a storage capacitor (Figure 1-1). Each storage cell contains one bit of information. This charge, however, leaks off the capacitor due to the sub-threshold current of the cell transistor. Therefore, the charge must be refreshed several times each second. Typical storage capacitance has a value of 20 to 50 fF.
Figue 1-1. Single transistor DRAM cell 
Operation of DRAM:
The memory cell is written to by placing a “1” or “0” charge into the capacitor cell. This is done during a write cycle by opening the cell transistor (gate to power supply or VCC) and presenting either VCC or 0V (ground) at the capacitor. The word line (gate of the transistor) is then held at ground to isolate the capacitor charge. This capacitor will be accessed for a new write, a read, or a refresh.
Figure 1-2 shows a simplified DRAM diagram. The gates of the memory cells are tied to the rows. The read (or write) of a DRAM is done in two main steps as illustrated in Figure 1-3. The row (X) and column (Y) addresses are presented on the same pads and multiplexed. The first step consists of validating the row addresses and the second step consists of validating the column addresses.
Figure 1-2. Simplified DRAM diagram 
Figure 1-3. DRAM access timing 
Typically, before any operation is performed each column capacitance is precharged high.
The cell is selected for a read/write operation by asserting its word line high (S = 1). This connects the storage capacitance to the bit line.
The write operation is performed by applying either high or low voltage to the bit line thus charging (write ‘1’) or discharging (write ‘0’) the storage capacitance through the access transistor.
During read operation there is a flow of charges between the storage capacitance C1 and the column capacitance, CC. As a result the column voltage either increases (read ‘1’) or decreases (read ‘0’) slightly. This difference can then be amplified by the sense amplifier.
Note that the read operation destroys the charge stored on the storage capacitance C1 (“destructive readout”). Therefore the data must be restored (refreshed) each time the read operation is performed. 
First Step: Row Addresses:
Row addresses are present on address pads and are internally validated by the RAS (Row Address Access) clock. A bar on top of the signal name means this signal is active when it is at a low level. The X addresses select one row through the row decode, while all the other non-selected rows remain at 0V. Each cell of the selected row is tied to a sense amplifier. A sense amplifier is a circuit that is able to recognize if a charge has been loaded into the capacitor of the memory cell, and to translate this charge or lack of charge into a 1 or 0. There are as many sense amplifiers as there are cells on a row. Each sense amplifier is connected to a column (Y address). In this first step all the cells of the entire row are read by the sense amplifier. This step is long and critical because the row has a high time constant due to the fact that it is formed by the gates of the memory cells. Also, the sense amplifier has to read a very weak charge (approximately 30 femtoFarads or 30fF).
Second Step: Column Addresses:
Following the first step, column addresses are present on the address pads and are internally validated by the Column Address Access (CAS) clock. Each selected memory cell has its data validated in a sense amplifier. Column access is fast. This step consists of transferring data present in the sense amplifier to the Dout pin through the column decode and the output buffer. This step consists of transferring data present in the sense amplifier to the Dout pin through the column decode and the output buffer. On memory data sheets, the access time from RAS is termed tRAC and the access time from CAS is listed as tCAC. On a typical standard DRAM of 60ns access time, tRAC = 60ns and tCAC = 15ns.
To maintain data integrity, it is necessary to refresh each DRAM memory cell. Each row of cells is refreshed every cycle. For example, if the product specification states, “Refresh cycle = 512 cycles per 8ms,” then there are 512 rows and each individual row must be refreshed every eight milliseconds. As explained above, during the row access step, all the cells from the same row are read by the sense amplifier. The sense amplifier has two roles. Since it holds information within the cell, it is able to transmit this data to the output buffer if it is selected by the column address. The sense amplifier is also able to re-transmit (write) the information into the memory cell. In this case, it “refreshes” the memory cell. When one row is selected, all the cells of that row are read by the sense amplifiers and all these cells are refreshed one at a time. Burst or distributed refresh methods can be used. Burst refresh is done by performing a series of refresh cycles until all rows have been accessed. For the example given above, this is done every 8ms. During the refresh, other commands are not allowed. Using the distributed method and the above example, a refresh is done every 12.6AZA?s (8ms divided by 512). Figure 1-1 shows these two modes.
Figure 1-1. Burst and distributed refresh
For standard DRAMs there are three ways to perform refresh cycles. They are RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. To perform a RAS-only refresh, a row address is put on the address lines and then RAS goes low. To perform a CAS-before-RAS refresh, CAS first goes low and then a refresh cycle is performed each time RAS goes low. To perform a hidden refresh the users does a read or write cycle and then brings RAS high and then low.
Varieties of DRAMs:
Compared with other memory ICs, DRAMs suffer from a speed problem. The on-chip circuitry required to read the data from each cell is inherently slow. As such, DRAM speeds have not kept pace with the increased clock speed of CPUs. To face this speed discrepancy, DRAMs have been branched into many sub-categories. Each features a variation of system interface circuitry with the intent of enhancing performance. Furthermore, each design attempts to answer needs of specific applications.
Figure 1-2 Varieties of DRAMs
Fast Page Mode DRAMs:
Fast Page Mode memory works faster than normal DRAM. The access time to memory cells is reduced. The addresses of the DRAM are multiplexed on the same package pins. When requested data is stored in the same row as the previous data, changing only the column address allows access to new data. With fast mode, data of same row can be accessed by changing the column address.
Cache DRAM was developed by Mitsubishi. This device integrates certain amount of main memory and certain amount of SRAM cache memory on the same chip. The transfer between DRAM and SRAM are performed in one clock cycle.
Technically, the EDRAM is a cache DRAM (CDRAM). Rather than integrate a separate SRAM cache, the EDRAM takes advantage of the internal architecture of a standard fast page mode DRAM, which has sense amplifiers that act like a SRAM cache when reading and accessing data.
Synchronous DRAMs (SDRAMs) are variant of DRAMs in which the read and write cycles are synchronized with the processor clock. This synchronization allows SDRAM to pipeline read and write requests. The speed of the SDRAM is rated in MHz rather than in nanoseconds. The SDRAM is designed with two separate banks. These two independent banks allow each bank to have different rows active at the same time. This allows concurrent access/refresh and recharge operations. A The clock is used to drive an internalA finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronousA DRAM, which does not have a synchronized interface .
Figure 1-1. 4Mbit SDRAM Block Diagram
The SDRAM is programmed using a mode register. The size of the mode register is equivalent to the number of address pins on the device and is written during a mode register set cycle. This mode register must be reprogrammed each time any of the programmable features have to be modified.
Double Data Rate DRAMs:
Double Data Rate DRAMs (DDR DRAMs) reads data of an SDRAM at two times the frequency clock. The device delivers data on both edges of the clock, doubling effective bandwidth at a given frequency.